Certain distributed processing systems use snoop bus interconnects to allow processing cores within the distributed processing systems to determine the status of transactions to shared memory resources. In particular, a memory controller places information on the snoop bus interconnect indicating in part which processing core currently has an active memory transaction being performed along with information about the memory transaction. The processing cores can then monitor the snoop bus interconnect to determine when relevant memory transactions are being performed with respect to the shared memory resources.
During operation of such a distributed processing system, the bandwidth for the snoop bus interconnect is a highly utilized resource that can limit performance. Although certain non-coherent memory transactions for processing cores, such as write-back or cast-out transactions for caches within the processing cores, are not relevant to other processing cores, snoop information for these non-coherent memory transactions is still output to the snoop bus interconnect because the associated data could be shared coherently by other caches in the distributed processing system. These non-coherent transactions are ordered within the global order of performance of all coherent transactions to the same data locations within the shared memory resources. As such, snoop information for these non-coherent transactions is placed on the snoop bus interconnect along with snoop information for coherent transactions by inserting the non-coherent snoop information within the sequence of coherent snoop information. Although the non-coherent snoop information is relevant only to the requester processing core for that non-coherent memory transaction and to the storage device it targets, this non-coherent snoop information still occupies a slot within the snoop bandwidth for all devices.
FIG. 1 (Prior Art) is a block diagram of an example embodiment 100 for a distributed processing system having multiple processing cores 104, a memory bus interconnect 102, a snoop bus interconnect 106, and a memory controller 108. The processing cores 104 are coupled to the memory bus interconnect 102 and to the snoop bus interconnect 106. A memory controller 108 is also coupled to the memory bus interconnect 102 and one or more shared memory devices 114. Memory transactions from the processing cores 104 are communicated through the memory bus interconnect 102 to the memory controller 108. The memory controller 108 includes a memory transaction controller 110 that controls the release of ordered memory transactions 118 from the processing cores 104 to the shared memory devices 114 through the memory device bus 116. The memory controller 108 also includes a snoop bus controller 112 that provides snoop messages 120 to the snoop bus interconnect 106. These snoop messages 120 include snoop information 122 and are ordered to correspond to the ordered memory transactions 118 being released on the memory device bus 116.
The ordered memory transactions 118 represent memory transactions directed to common data locations within the memory devices 114, and these ordered memory transactions 118 are released in order to the memory device bus 116. These ordered memory transactions 118 include coherent memory transactions (e.g., CMT1, CMT2, CMT3, . . . ) and non-coherent memory transactions (e.g., NCMT1, NCMT2, . . . ). The coherent memory transactions (e.g., CMT1, CMT2, CMT3, . . . ) relate to memory transactions issued by a requester processing core that are potentially relevant to multiple processing cores, and non-coherent memory transactions (e.g., NCMT1, NCMT2, . . . ) relate to memory transactions issued by a requester processing core that are only relevant to that requesting processing core. The snoop information 122 is associated with the ordered memory transactions 118 and is similarly ordered. As such, this snoop information 122 includes snoop information corresponding to the coherent memory transactions (e.g., SN-CMT1, SN-CMT2, SN-CMT3, . . . ) and snoop information corresponding to the non-coherent memory transactions (e.g., SN-NCMT1, SN-NCMT2, . . . ). This snoop information 122 for each memory transaction is released as a snoop message 120 to the snoop bus interconnect 106 during snoop cycles for the distributed processing system 100. It is noted that the snoop message 120 can be an N-bit snoop message and that the snoop bus interconnect 106 can be implemented using N physical wires, where N is a selected integer number.